NoC Interface for a Protocol Processor

In this paper we present our design and implementation of Network-on-Chip (NoC) support into our TACO protocol processor architecture. Our signaling scheme is Virtual Component Interface standard (VCI) compliant. Due to the dataand I/O-intensive nature of protocol processing, memory access from I/O logic plays a key role in NoC interface design. We have addressed this problem by using dual-port memory for protocol data units (PDUs) and a separate single port memory for other user data. We evaluated our NoC interface with VHDL synthesis of a case study in IPv6 processing. Based on our simulations and synthesis, the logic part is able to operate at 200 MHz in 0.18 μm CMOS technology. Adding a NoC interface into our architecture did not considerably increase area and power costs.